MORA Development Box
The MORA Development Box simplifies the process of creating RF signal processing capabilities and expedites the integration of existing applications within the MORA space. Using the hardware-agnostic helux Core, a combination of software libraries and firmware modules, the MORA Development Box integrates the high-performing Epiq Solutions Sidekiq X4 with a Xilinx ZCU102 FPGA (development board) to provide MORA-compliant interfaces for the VICTORY Data Bus (VBD) and MORA Low Latency Bus (ML2B).
For an even more robust system, additional helux graphical tools can be added, including the MORA Explorer to visualize, explore, and control MORA-enabled hardware and the MSRP Generator to create, view, and modify MORA Signal Resource Profiles (MSRP). Together, the MORA Development Box and optional helux Tools offer an affordable, user-friendly solution for developers in the MORA community.
Front
RF Transceiver Specifications
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4 RX and 4 TX channels
(phase coherent or two-phase coherent pairs) -
RF Tuning Range: 1 MHz to 6 GHz
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Sample Width: 16-bit ADCs, 14-bit DACs
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Channel Bandwidth: Up to 200 MHz
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Instantaneous Bandwidth: 800 MHz
RF Input Specifications
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1 PPS for data timestamping
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10 MHz reference for phase locking to external source
Rear
Network Interfaces
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ML2B - 40GbE or 4x 10GbE via 4x SFP+ cage
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VDB - 1GbE via RJ45
Open Standards Compliance
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MORA 2.4, updated as spec evolves
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VITA 49.2 (upon request)
Dimensions and Weight
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14in x 13.25in x 4.1in (LxWxH)
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7.78 lbs (3.53 kg)